N-channel JFET

An N-JFET (junction field-effect transistor) is a bar of N-type silicon, the channel, with a contact at each end: the source, where the electrons enter, and the drain, where they leave. Conventional current therefore flows from drain to source. Along the channel sits a P-type region, the gate, which forms a PN junction with it. That junction is kept reverse-biased, so the gate draws only leakage: at most 1 nA for a J111 at $V_{GS} = -15$ V. A reverse-biased junction grows a depletion region, a layer emptied of free carriers that does not conduct, and here that layer grows into the channel. There is no insulating layer as in a MOSFET: the gate is one side of a diode. In the symbol the arrow on the gate points in, from the P gate to the N channel, the direction of that diode.

With the gate at the source voltage the channel is wide open, so the JFET conducts with no drive at all: it is normally on, the opposite of an NPN or an enhancement MOSFET. Taking the gate negative widens the depletion layers and narrows the channel. At the pinch-off voltage $V_P$ they meet across the whole channel and the current stops. A datasheet calls this voltage $V_{GS(off)}$, the gate-source cutoff voltage. It is negative for an N-channel part: -3 to -10 V for a J111, read at $I_D = 1$ µA and $V_{DS} = 5$ V.

The drain voltage pinches the channel too. The gate-channel voltage is $V_{GS}$ at the source end but $V_{GD} = V_{GS} - V_{DS}$ at the drain end, more negative, so the channel is narrowest at the drain. Once $V_{DS}$ reaches $V_{GS} - V_P$, the drain end is pinched and the current stops growing with $V_{DS}$. The JFET is then a current source, set by the gate alone.

In that flat region the drain current follows Shockley's square law:

$I_{DSS}$ is the drain current with the gate shorted to the source, measured in the flat region: at $V_{DS} = 15$ V and in short pulses for a J111. It is the most the channel passes while the gate stays reverse-biased. The law is a parabola: halfway to pinch-off, at $V_{GS} = V_P / 2$, the current is already down to a quarter of $I_{DSS}$.

Below that edge the channel is open at both ends and behaves as a resistor whose value the gate sets:

For a small $V_{DS}$ the squared term drops out. The conductance of the channel is then a straight line in $V_{GS}$ that reaches zero at $V_P$:

$r_{DS0}$ is the resistance at $V_{GS} = 0$, the $r_{DS(on)}$ of a datasheet: at most 30 Ω for a J111, measured with $V_{DS} \le 0.1$ V. These are the equations of an enhancement MOSFET, whose saturation law is $I_D = \tfrac12 k (V_{GS} - V_{th})^2$, with $k$ a constant of the part in A/V² and $V_{th}$ its threshold. Putting $V_P$ in place of $V_{th}$ and $k = 2 I_{DSS} / V_P^2$ gives the JFET laws above, so the MOSFET square law applies with those two substitutions.

Regions of operation

"Saturation" is the flat current-source region, the equivalent of the BJT's active region, as for a MOSFET. The fully-on JFET switch sits in the ohmic region. "Pinch-off" names two things: the gate voltage $V_P$ that closes the whole channel, and the pinching of the drain end that starts the saturation region; Siliconix writes $V_{GS(off)}$ for the first to avoid the clash. "Linear region" means the ohmic region in a textbook, while power-MOSFET application notes say "linear mode" for the saturation region.

How far the drain current moves per volt on the gate, the transconductance $g_m$, follows from the square law:

$g_{m0}$ is the value at $V_{GS} = 0$. An amplifier datasheet prints it as $|y_{fs}|$ or $g_{fs}$: 1 to 5 mS for a 2N5457 at $V_{DS} = 15$ V and 1 kHz. It also equals the channel conductance at $V_{GS} = 0$, so a JFET with a low $r_{DS(on)}$ has a high $g_{m0}$. For the part of the first and third simulations below ($I_{DSS} = 3$ mA, $V_P = -1.5$ V), $g_{m0} = 4$ mS, and $g_m = 2.51$ mS at 1.185 mA. An NPN at the same current has $I_C / V_T = 45.9$ mS, about 18 times more, so a JFET stage gains far less. What it offers instead is an input that draws next to nothing.

Where a JFET is the right part

• Voltage-controlled resistor. Between 0 V and $V_P$ the gate sets the channel's resistance over a range of 10:1 or more. The AM modulator of this site uses a J111 this way.
• Two-part current source. With the gate tied to the source, or to the bottom of a source resistor, the current holds while the supply varies, and the gate needs no supply of its own. A current-regulator diode is this circuit in one package.
• Analog switch. On at $V_{GS} = 0$, with $r_{DS(on)}$ at most 30 Ω for a J111; off below $V_{GS(off)}$, with 1 nA of leakage. The J111 datasheet names analog switching, sample-and-hold circuits and chopper-stabilised amplifiers as its uses.
• Low-noise, high-impedance input. The gate of an LSK170 draws at most 0.5 nA at 1 mA and $V_{DG} = 10$ V: 0.5 mV across a 1 MΩ source. An NPN at 1 mA with $\beta = 100$ would need 10 µA of base current, 10 V across the same 1 MΩ. The LSK170's voltage noise is 0.9 nV/√Hz typical at 1 kHz and 2 mA, the thermal noise of a 49 Ω resistor, which counts with a low-impedance source. With a high-impedance source the gate current $I_G$ counts instead: its shot noise, $\sqrt{2 q I_G}$ with $q$ the charge of the electron, is 13 fA/√Hz at 0.5 nA, or 13 nV/√Hz across 1 MΩ, a tenth of that resistor's own 129 nV/√Hz. The TL082 op-amp of the lab bench has a JFET pair at its inputs for the same reason.

Switch JFETs and amplifier JFETs. The J111, J112 and J113 guarantee what a switch needs: $r_{DS(on)}$ (30, 50 and 100 Ω at most), $V_{GS(off)}$, leakage and capacitance. Their $g_{fs}$ appears only as typical curves. The 2N5457 guarantees what an amplifier needs, $|y_{fs}|$ of 1 to 5 mS and $|y_{os}|$ of 50 µS at most, but no $r_{DS(on)}$. A design picks the part whose datasheet guarantees the numbers it depends on.

Low-noise JFETs such as the LSK170 add noise to the guarantees: 1.9 nV/√Hz at most at 1 kHz and 4.0 at 10 Hz ($V_{DS} = 10$ V, $I_D = 2$ mA). Their input capacitance is large, 20 pF typical for the LSK170 ($V_{DS} = 15$ V, $I_D = 100$ µA, 1 MHz).

The P-channel JFET is the same part with every polarity reversed: $V_{GS(off)}$ is positive, +1 to +4 V for a J176 (at $I_D = -10$ nA, $V_{DS} = -15$ V), and the source is the terminal at the higher voltage. The depletion MOSFET is normally on too, but its gate is insulated, so it can be driven positive without drawing current.

Meter check. On the diode range, red lead on the gate: 0.6 to 0.7 V to the drain and to the source, the gate junction conducting; nothing with the leads swapped. Between drain and source the meter reads nearly a short both ways, at most about 30 Ω on the resistance range for a J111: the channel conducts with nothing on the gate. A drop with the red lead on the gate means an N channel; a P-channel part shows it with the black lead there. The meter cannot tell drain from source on a symmetric part such as the J111; its pinout drawing decides (D-S-G, flat face toward the viewer, legs down). A floating gate can keep charge from the previous test and pinch the channel, so touching the gate to the source first makes the readings steady.

First build. The current source of the first simulation, with a J111: drain to +15 V, gate to ground, 1 kΩ from source to ground. A voltmeter across the 1 kΩ reads both $|V_{GS}|$ and the current in milliamps: from about 2.0 V for a -3 V part with 20 mA to about 8.0 V for a -10 V part with 200 mA, so 56 mW at most in the JFET. The reading holds as the supply comes down, until the drain gets within $|V_P|$ of the gate. With 1 MΩ in place of the 1 kΩ, only a few microamps can flow, and the source rises almost to $|V_P|$: 4.95 V for a -5 V part.

The two readings give $I_{DSS}$ without ever passing it through the part. For a J111 that reads 3.9 V across 1 kΩ and 4.95 V across 1 MΩ:

The division by a small number makes the result sensitive: taking $|V_P|$ as 5.00 V instead of 4.95 V gives 81 mA. It is an estimate, close enough to tell a 30 mA part from a 100 mA one. By the square law this part has $r_{DS0} = 4.95\ \text{V} / (2 \times 87\ \text{mA}) \approx 28\ \Omega$, inside the 30 Ω limit.